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1 of 19 rev: 070706 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . features 8-bit 8051-compatible microcontroller adapts to task at hand 8 or 32 kbytes of nonvolatile ram for program and/or data memory storage initial downloading of software in end system via on-chip serial port capable of modifying its own program and/or data memory in end use crashproof operation maintains all nonvolatile resources for 10 years in the absence of v cc at room temperature power-fail reset early warning power-fail interrupt watchdog timer software security feature executes encrypted software to prevent unauthorized disclosure on-chip, full-duplex serial i/o ports two on-chip timer/event counters 32 parallel i/o lines compatible with industry standard 8051 instruction set and pinout optional permanently powered real-time clock (ds5000t) pin assignment description the ds5000(t) soft microcontroller module is a fully 8051-compatible 8-bit cmos microcontroller that offers ?softness? in all aspects of its application. this is accomplished through th e comprehensive use of nonvolatile technology to pres erve all information in the absence of system v cc . the internal program/data memory space is implemented using either 8 or 32 kbytes of nonvolatile cmos sram. furthermore, internal data registers and key configur ation registers are also nonvolatile. an optional real- time clock (rtc) gives permanently powered timek eeping. the clock keeps time to a hundredth of a second using an on-board crystal. note: this data sheet provides ordering information, pinout, and electrical spec ifications. refer to the secure microcontroller user?s guide for operating information. ds5000(t) soft microcontroller module www.maxim-ic.com 1 p1.0 2 p1.1 3 p1.2 4 p1.3 5 p1.4 6 p1.5 7 p1.6 8 p1.7 9 rst 10 rxd p3.0 11 txd p3.1 12 int0 p3.2 13 int1 p3.3 14 t0 p3.4 15 t1 p3.5 16 wr p3.6 17 rd p3.7 18 xtal2 19 xtal1 20 gnd v cc 40 p0.0 ad0 39 p0.1 ad1 38 p0.2 ad2 37 p0.3 ad3 36 p0.4 ad4 35 p0.5 ad5 34 p0.6 ad6 33 p0.7 ad7 32 e a 31 a le 30 psen 29 p2.7 a15 28 p2.6 a14 27 p2.5 a13 26 p2.4 a12 25 p2.3 a11 24 p2.2 a10 23 p2.1 a9 22 p2.0 a8 21 40-pin enca p sulated packa g e ds5000(t)
ds5000(t) 2 of 19 ordering information part ram size (kb) max crystal speed (mhz) timekeeping? ds5000 -32-16 32 16 no ds5000-32-16+ 32 16 no ds5000t -32-16 32 16 yes DS5000T-32-16+ 32 16 yes + denotes a lead-free package. ds5000(t) block diagram figure 1
ds5000(t) 3 of 19 pin description pin name function 1?8 p1.0?p1.7 general-purpose i/o port 1 9 rst active-high reset input. a logic 1 applied to this pin will activate a reset state. this pin is pulled down internally so this pin can be left unconnected if not used. 10 p3.0/rxd general-purpose i/o port pin 3.0/receive signal for on-board uart. this pin should not be connected directly to a pc com port. 11 p3.1/txd general-purpose i/o port pin 3.1/transmit signal for on-board uart. this pin should not be connected directly to a pc com port. 12 p3.2/ int0 general-purpose i/o port pin 3.2/active-low external interrupt 0 13 p3.3/ int1 general-purpose i/o port pin 3.3/active-low external interrupt 1 14 p3.4/t0 general-purpose i/o port pin 3.4/timer 0 input 15 p3.5/t1 general-purpose i/o port pin 3.5/timer 1 input 16 p3.6/ wr general-purpose i/o port pin 3.6/active -low write strobe for expanded bus operation 17 p3.7/ rd general-purpose i/o port pin 3.7/active -low read strobe for expanded bus operation 18, 19 xtal2, xtal1 crystal connection. used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amplifier and xtal2 is the output. 20 gnd logic ground 21?28 p2.0?p2.7/ a8?a15 general-purpose i/o port 2/msb of the expanded address bus 29 psen active-low program store enable. used to enable an external program memory when using the expanded bus. it is normally an output and should be unconnected if not used. psen also is used to invoke the bootstrap loader. at this time, psen is pulled down externally. this should only be done once the ds5000(t) is already in a reset state. the device that pulls down should be open drain since it must not interfere with psen under normal operation. 30 ale address latch enable. used to demultiplex the multiplexed expanded address/data bus on port 0. this pin is normally connected to the clock input on a ?373 type transparent latch. when using a parallel programmer, this pin also assumes the prog function for programming pulses. 31 ea active-low external access. this pin forces the ds5000(t) to behave like an 8031. no internal memory (or clock) is available when this pin is at a logic low. since this pin is pulled down internally, it should be connected to +5v to use nv ram. in a parallel programmer, this pin also serves as v pp for super voltage pulses. 32-39 p0.7?p0.0/ ad7?ad0 general-purpose i/o port 0/multiplexed expa nded address/data bus. this port is open drain and cannot drive a logic 1. it requires external pullups. when used in the multiplexed expanded address data/bus mode, this pin does not require pullups. 40 v cc +5v power supply
ds5000(t) 4 of 19 instruction set the ds5000(t) executes an instruc tion set which is object code-compa tible with the i ndustry standard 8051 microcontroller. as a result, so ftware development packages that have been written for the 8051, including cross-assemblers, high-lev el language compilers, and debugging tools, are compatible with the ds5000(t). a complete description for the ds5000( t) instruction set is available in secure microcontroller user?s guide . memory organization figure 2 illustrates the address spaces, which are acces sed by the ds5000(t). as illustrated in the figure, separate address spaces exist for program and data me mory. since the basic addressing capability of the machine is 16 bits, a maximum of 64 kbytes of progr am memory and 64 kbytes of data memory can be accessed by the ds5000(t) cpu. the 8- or 32-kbyte ram area inside of the ds 5000(t) can be used to contain both program and data memory. the real-time clock (rtc) in the ds5000t is reached in the memory map by setting a sfr bit. the mcon.2 bit (ece2) is used to select an alternat e data memory map. while ece2 = 1, all movxs will be routed to this alternate memory map. the rtc is a serial device that resides in this area. a full description of the rtc access and ex ample software is given in the secure microcontroller user?s guide . if the ece2 bit is set on a ds5000 without a time keeper, the movxs will simply go to a nonexistent memory. software execution woul d not be affected otherwise.
ds5000(t) 5 of 19 ds5000(t) logical address spaces figure 2 program loading the program load modes allow initialization of th e nv ram program/data memory. this initialization may be performed in one of two ways: 1. serial program loading that can perform bootst rap loading of the ds5000(t) . this feature allows the loading of the application program to be de layed until the ds5000(t) is installed in the end system. dallas semiconductor strongly recommends the use of serial program loading because of its versatility and ease of use. 2. parallel program load cycles that perform the in itial loading from parallel address/data information presented on the i/o port pins. this mode is tim ing-set compatible with the 8751h microcontroller programming mode. the ds5000(t) is placed in its pr ogram load configuration by simulta neously applying a logic 1 to the rst pin and forcing the psen line to a logic 0 level. immediat ely following this action, the ds5000(t) will look for a parallel program load pulse, or a serial ascii carriage return (0dh) character received at 9600, 2400, 1200, or 300 bps over the serial port. the hardware configurations used to select these modes of oper ation are illustrated in figure 3.
ds5000(t) 6 of 19 program loading configurations figure 3 table 1 summarizes the selection of the available pa rallel program load cycles. the timing associated with these cycles is illustra ted in the electrical specs. serial bootstrap loader the serial program load mode is the easiest, fastest, most reliab le, and most complete method of initially loading application software into the ds5000(t) nonvolatile ram. communication can be performed over a standard asynchr onous serial communications port. a typical application would use a simple rs232c serial interface to program the ds5000( t) as a final production procedure. the hardware configuration required for the serial program load mode is illustrated in figure 3. port pins 2.7 and 2.6 must be either open or pulled high to avoid placing the ds5000(t) in a parallel load cycle. although an 11.0592 mhz crystal is shown in figure 3, a variety of crystal frequenc ies and loader baud rates are supported, shown in table 2. the seri al loader is designed to operate across a 3-wire interface from a standard uart. the receive, transmit, and ground wires are all that are necessary to establish communication with the ds5000(t). the serial bootstrap loader implemen ts an easy-to-use command line in terface that allows an application program in an intel hex representation to be loaded in to and read back from the device. intel hex is the typical format which existing 8051 cross-assemblers output. the serial lo ader responds to single character commands, which are summarized below:
ds5000(t) 7 of 19 command function c return crc-16 checksum of embedded ram d dump intel hex file f fill embedded ram block with constant k load 40-bit encryption key l load intel hex file r read mcon register t trace (echo) incoming intel hex data u clear security lock v verify embedded ram with incoming intel hex w write mcon register z set security lock p put a value to a port g get a value from a port parallel prog ram load cycles table 1 mode rst psen prog ea p2.7 p2.6 p2.5 program 1 0 0 v pp 1 0 x security set 1 0 0 v pp 1 1 x verify 1 x x 1 0 0 x prog expanded 1 0 0 v pp 0 1 0 verify expanded 1 0 1 1 0 1 0 prog mcon or key registers 1 0 0 v pp 0 1 1 verify mcon registers 1 0 1 1 0 1 1 the parallel program cycle is used to load a byte of data into a register or memory location within the ds5000(t). the verify cycle is used to read this byt e back for comparison with the originally loaded value to verify proper loading. the security set cycle may be used to enable and the software security feature of the ds5000(t). one may also enter bytes for the mcon register or for the five encryption registers using the program mcon cycle. when using th is cycle, the absolute register address must be presented at ports 1 and 2 as in the normal program cycle (port 2 should be 00h). the mcon contents can likewise be verified using the verify mcon cycle. when the ds5000(t) first detects a para llel program strobe pulse or a s ecurity set strobe pulse while in the program load mode following a power-on rese t, the internal hardwa re of the ds5000(t) is initialized so that an existing 4-kbyte program can be programmed into a ds5000 (t) with little or no modification. this initialization au tomatically sets the range address for 8 kbytes and maps the lowest 4- kbyte bank of embedded ram as program memory. the next 4 kbytes of embedded ram are mapped as data memory. in order to program more than 4 kbytes of program code, the progr am/verify expanded cycles can be used. up to 32 kbytes of program code can be en tered and verified. note that the expanded 32-kbyte program/ verify cycles take much longer th an the normal 4-kbyte program/verify cycles.
ds5000(t) 8 of 19 a typical parallel loadi ng session would follow this procedure. first, set the contents of the mcon register with the correct range and partition onl y if using expanded progr amming cycles. next, the encryption registers can be loaded to enable encryption of the program/data memory (not required). then, program the ds5000(t) using either normal or expande d program cycles and check the memory contents using verify cycles. the last operation would be to tu rn on the security lock f eature by either a security set cycle or by explicitly writing to the mcon register and setting mcon.0 to a 1. serial loader baud rates for different crysta l frequencies table 2 baud rate crystal freq (mhz) 300 1200 2400 9600 19200 57600 14.7456 y y y y 11.0592 y y y y y y 9.21600 y y y y 7.37280 y y y y 5.52960 y y y y 1.84320 y y y y additional information refer to the secure microcontroller user?s guide for a complete description for all operational aspects of the ds5000(t). development support the ds89c450-k00 evaluation kit ( www.maxim-ic.com/ds89c450evkit ) can be used to develop and test user code. it allows the user to download intel hex-formatted code to the ds5000(t) from a pc. refer to the secure microcontroller user?s guide for more information.
ds5000(t) 9 of 19 absolute maxi mum ratings voltage on any pin relative to ground????????????????????.-0.3v to +7.0v operating temperature??????????????????????????.?.0c to +70c storage temperature???????????????????????????...-40c to +70c soldering temperature.????????????????see ipc/ jedec j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods of time may affect device rel iability. dc characteristics (t a =0 c to 70 c; v cc =5v 5%) parameter symbol min typ max units notes input low voltage v il -0.3 0.8 v 1 input high voltage v ih1 2.0 v cc +0.3 v 1 input high voltage rst, xtal1 v ih2 3.5 v cc +0.3 v 1 output low voltage @ i ol =1.6 ma (ports 1, 2, 3) v ol1 0.15 0.45 v output low voltage @ i ol =3.2 ma (ports 0, ale, psen ) v ol2 0.15 0.45 v 1 output high voltage @ i oh =-80 a (ports 1, 2, 3) v oh1 2.4 4.8 v 1 output high voltage @ i oh =-400 a (ports 0, ale, psen ) v oh2 2.4 4.8 v 1 input low current v in = 0.45v (ports 1, 2, 3) i il -50 a transition current; 1 to 0 v in =2.0v (ports 1, 2, 3) i tl -500 a input leakage current 0.45 < v in < v cc (port 0) i l 10 a rst, ea pulldown resistor r re 40 125 k ? stop mode current i sm 80 a 4 power-fail warning voltage v pfw 4.15 4.6 4.75 v 1 minimum operating voltage v ccmin 4.05 4.5 4.65 v 1 programming supply voltage (parallel program mode) v pp 12.5 13 v 1 program supply current i pp 15 20 ma operating current ds5000-8k @ 8mhz ds5000-32k @ 12 mhz ds5000(t)-32-16 @ 16 mhz i cc 25.2 35.7 45.6 43 48 54 ma 2 idle mode current @ 12 mhz i cc 4.5 6.2 ma 3
ds5000(t) 10 of 19 ac characteristics: expanded bus mode timing specifications (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 1 oscillator frequency 1/t clk 1.0 16 mhz 2 ale pulse width t alpw 2t clk -40 ns 3 address valid to ale low t avall t clk -40 ns 4 address hold after ale low t avaav t clk -35 ns 5 ale low to valid instr. in @ 12 mhz @ 16 mhz t allvi 4t clk -150 4t clk -90 ns ns 6 ale low to psen low t allpsl t clk -25 ns 7 psen pulse width t pspw 3t clk -35 ns 8 psen low to valid instr. in @ 12 mhz @ 16 mhz t pslvi 3t clk -150 3t clk -90 ns ns 9 input instr. hold after psen going high t psiv 0 ns 10 input instr. float after psen going high t psix t clk -20 ns 11 address hold after psen going high t psav t clk -8 ns 12 address valid to valid instr. in @ 12 mhz @ 16 mhz t avvi 5t clk -150 5t clk -90 ns ns 13 psen low to address float t pslaz 0 ns 14 rd pulse width t rdpw 6t clk -100 ns 15 wr pulse width t wrpw 6t clk -100 ns 16 rd low to valid data in @ 12 mhz @ 16 mhz t rdldv 5t clk -165 5t clk -105 ns ns 17 data hold after rd high t rdhdv 0 ns 18 data float after rd high t rdhdz 2t clk -70 ns 19 ale low to valid data in @ 12 mhz @ 16 mhz t allvd 8 clk -150 8t clk -90 ns ns 20 valid addr. to valid data in @ 12 mhz @ 16 mhz t avdv 9t clk -165 9t clk -105 ns ns 21 ale low to rd or wr low t allrdl 3t clk -50 3t clk +50 ns 22 address valid to rd or wr low t avrdl 4t clk -130 ns 23 data valid to wr going low t dvwrl t clk -60 ns 24 data valid to wr high @ 12 mhz @ 16 mhz t dvwrh 7t clk -150 7t clk -90 ns ns 25 data valid after wr high t wrhdv t clk -50 ns 26 rd low to address float t rdlaz 0 ns 27 rd or wr high to ale high t rdhalh t clk -40 t clk +50 ns
ds5000(t) 11 of 19 expanded program memory read cycle expanded data memory read cycle
ds5000(t) 12 of 19 expanded data memory write cycle external clock timing
ds5000(t) 13 of 19 ac characteristics (cont'd) external clock drive (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 28 external clock high time @ 12 mhz @ 16 mhz t clkhpw 20 15 ns ns 29 external clock low time @ 12 mhz @ 16 mhz t clklpw 20 15 ns ns 30 external clock rise time @ 12 mhz @ 16 mhz t clkr 20 15 ns ns 31 external clock fall time @ 12 mhz @ 16 mhz t clkf 20 15 ns ns ac characteristics (cont'd) serial port timing - mode 0 (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 35 serial port cycle time t spclk 12t clk s 36 output data setup to rising clock edge t doch 10t clk -133 ns 37 output data hold after rising clock edge t chdo 2t clk -117 ns 38 clock rising edge to input data valid t chdv 10t clk -133 ns 39 input data hold afte r rising clock edge t chdiv 0 ns serial port timing - mode 0
ds5000(t) 14 of 19 ac characteristics (cont'd) power cycling timing (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 32 slew rate from v ccmin to 3.3v t f 40 s 33 crystal start-up time t csu (note 5) 34 power-on reset delay t por 21504 t clk power cycle timing
ds5000(t) 15 of 19 ac characteristics (cont'd) parallel program load timing (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 40 oscillator frequency 1/t clk 1.0 12.0 mhz 41 address setup to prog low t avprl 0 42 address hold after prog high t prhav 0 43 data setup to prog low t dvprl 0 44 data hold after prog high t prhdv 0 45 p2.7, 2.6, 2.5 setup to v pp t p27hvp 0 46 v pp setup to prog low t vphprl 0 47 v pp hold after prog low t prhvpl 0 48 prog width low t prw 2400 t clk 49 data output from address valid t avdv 48 1800* t clk 50 data output from p2.7 low t dvp27l 48 1800* t clk 51 data float after p2.7 high t p27hdz 0 48 1800* t clk 52 delay to reset/ psen active after power on t porpv 21504 t clk 53 reset/ psen active (or verify inactive) to v pp high t ravph 1200 t clk 54 v pp inactive (between program cycles) t vpppc 1200 t clk 55 verify active time t vft 48 2400* t clk * second set of numbers refers to ex panded memory programming up to 32k bytes.
ds5000(t) 16 of 19 parallel program load timing capacitance (test frequency=1mhz; t a =25 c) parameter symbol min typ max units notes output capacitance c o 10 pf input capacitance c i 10 pf
ds5000(t) 17 of 19 ds5000(t) typical i cc vs. frequency normal operation is measured using: 1) external crystals on xtal1 and 2 2) all port pins disconnected 3) rst=0 volts and ea=v cc 4) part performing endless l oop writing to internal memory idle mode operation is measured using: 1) external clock source at xtal1; xtal2 floating 2) all port pins disconnected 3) rst=0 volts and ea=v cc 4) part set in idle mode by software
ds5000(t) 18 of 19 notes: 1. all voltages are referenced to ground. 2. maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10 ns, v il = 0.5v; xtal2 disconnected; ea = rst = port0 = v cc . 3. idle mode i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10 ns, v il = 0.5v; xtal2 disconnected; ea = port0 = v cc , rst = v ss . 4. stop mode i cc is measured with all output pins disconnected; ea = port0 = v cc ; xtal2 not connected; rst = v ss . 5. crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. the user should check with the cr ystal vendor for the worst case spec on this time. package drawing inches dim min max a in. 2.080 2.100 b in. 0.680 0.700 c in. 0.290 0.325 d in. 0.090 0.110 e in. 0.030 0.060 f in. 0.145 0.185 g in. 0.016 0.020 h in. 0.590 0.610 i in. 0.009 0.015
ds5000(t) 19 of 19 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. data sheet revision summary revision description 072095 to 072496 corrected figure 3 to show rst active high. added data sheet revision summary section. 112299 converted from interleaf to word. 070706 page 1: features added ?at room temperature? to ?maintai ns all nonvolatile resources up to 10 years in the absence of v cc ? bullet. page 2: ordering information removed 8kb parts from list; a dded 32kb and lead-free packages. page 8: development support updated paragraph to reflect availabi lity of ds89c450-k00 evaluation kit, not ds5000tk. page 9: absolute maximum ratings changed ?260 c for 10 seconds? to ?see ipc/jedec j-std-020 specification.? pages 1, 4, 8: replaced references to ?user?s guide section of secure microcontroller data book? with ?s ecure microcontroller user?s guide.?

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